以下文章来源于半导体百科 ,作者John H. Lau
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转载自半导体百科
作者:John H. Lau
图1:Potential application and high-volume manufacturing of 3D IC integration
存储芯片堆叠
图1最左端图示是Samsung公司在2006年发布的最简单的存储芯片堆叠示意图。这些芯片可能是DRAM(动态随机存取存储器)或I/O数量少于100的NAND闪存(确切地说是78个)。很重要的一点是,这种存储芯片附在有机基板上,即使采用八个芯片堆叠,它们的总厚度(560μm)仍小于普通芯片的厚度。遗憾的是,由于成本问题和引线键合技术的竞争,使用TSV(Through Silicon Via,硅通孔技术)的存储器芯片堆叠目前尚未针对消费产品进行批量生产。目前,Samsung正在开发的下一代服务器产品,很可能考虑采用DDR4(双信道四次同步动态随机存取内存)SDRAM(同步动态存储器)。
宽I / O存储或逻辑堆叠
宽I / O DRAM(HMC)
无源转接板的宽I / O接口(2.5DIC封装)
TSV时代之前的技术流程
TSV时代的技术流程
图2:Critical steps and ownerships for (face-to-back) wide I/O memory using the TSVvia-middle fabrication process.
图3:Critical steps and ownerships for (face-to-face) wide I/O memory using the TSVvia-middle fabrication process.
B)谁负责MEOL工艺
对于HMC中DRAMs和存储.芯片堆叠的厚度,以及考虑到有源和无源转接板的厚度,所有制造的TSV都是盲孔。盲孔TSV工艺之后是焊料凸点/临时粘合/减薄/ TSV露点/薄晶圆支撑转移/剥离/清洁,这些过程统称为MEOL(生产线的中端)。对于这项工作,除了纵向一体化公司公司(例如,TSMC和Samsung集团),最好由OSAT完成MEOL流程。
C)量产3D封装的关键步骤分工
C.1)TSV Via-Middle工艺制造宽I / O存储器(面对背):图2显示了该工艺的关键步骤和制备工厂。在FEOL(用于对器件进行图案化)和MOL(用于形成金属接触)之后,通过五个关键步骤制造TSVs,即通孔制造。通孔是由深反应等离子蚀刻形成的(DRIE),电介质是通过等离子体增强化学气相沉积的(PECVD),阻挡层和种子层通过物理气相沉积(PVD),使用电镀铜填充和化学机械抛光(CMP)去除覆盖的铜。这些步骤之后是金属层的堆积,最后是钝化/开口(BEOL)。所有这些步骤都应在fab中完成。
C.2)TSV Via-Middle工艺制造宽I / O存储器(面对面):FEOL,MOL,TSV和BEOL过程与TSV via-middle(面对背)工艺流程完全相同。但是,接下来的工艺流程是不同的。TSV晶片不是在UBM后使用C4技术焊接到载体晶片上,而是临时连接到载体#1。然后,对TSV晶片进行背面研磨,并完成Cu显露和UBM。这些步骤之后进行C4工艺,并临时粘合到第二个载体#2。然后,将载体#1从TSV晶片上剥离下来,并进行C2W(面对面)键合。在C2W键合之后,将载体#2从TSV晶片上剥离。随后将TSV晶片切成单独的TSV模块。将该TSV模块回流焊接到封装基板上,然后进行测试。关键步骤如图3所示。
C.3)TSV Via-Last工艺(从背面)制造宽I / O存储器(面对背):图4显示了该工艺的关键步骤和制备工厂。在FEOL(对器件进行图案化),MOL(形成金属接触)和BEOL(构建金属层以及钝化/开口)之后进行UBM制备和C4工艺。然后,将该结构临时和载体晶片键合。再进行背面研磨,TSV制造和钝化/开口以及UBM。
C.4)TSV Via-Last工艺(从背面)制造宽I / O存储器(面对面):FEOL,MOL和BEOL工艺与和面对背TSV via-last(从背面)过程完全相同。但是,对于面对面情况而言,在UBM步骤之后,器件晶片临时粘合到载体#1如图5所示。然后,对背面进行背面研磨,TSV加工和钝化/开口处理。在这些过程之后,制备UBM,进行C4工艺,并临时粘合至载体#2。然后完成与载体#1的剥离。
图5:Critical steps and ownerships for (face-to-face) wide I/O memory using the TSVvia-last from the backside fabrication process.
C.5)TSV Via-Middle工艺制造宽I / O DRAM:在DRAM和SoC/logic晶片的FEOL,MOL,TSV和BEOL之后,SoC /logic晶圆将按照图2(C.1)所示的面对背,或图3 (C.2)面对面工艺步骤进行操作。对于DRAM,首先要进行UBM,然后是整个晶圆的微凸点工艺。在这些过程之后,将临时粘合到载体晶片,进行背面研磨减薄,铜暴露和UBM。再依次进行载体晶圆剥离和将TSV DRAM晶圆切成单个TSV DRAM芯片,如图6所示。
图6:Critical steps and ownerships for wide I/O DRAM using the TSV via-middlefabrication process.
C.6)TSV Via-Middle工艺制造宽储存器芯片堆叠:存储器芯片(DRAM或NAND闪存)堆叠的关键步骤和制备工厂与宽I / O DRAM情况完全相同,如图6(C.5)所示。然而,不同于宽I / O DRAM情况下采用C2W键合,内存芯片堆叠是通过首先堆叠各个TSV芯片然后将它们连接到封装基板上并且采用灌胶成型来实现的。在这些步骤之后,将TSV存储器芯片堆叠模块连接到印刷电路板上,例如双列直插式存储器模块(RDIMM)。
C.7)2.5D IC封装技术制备TSV / RDL无源转接板:图7显示了关键步骤和制备工厂。在一块dummy硅(无有源器件)上沉积钝化层之后,制作TSV,构建RDL并进行钝化/开口。在UBM之后,将TSV晶片临时粘合到载体#1。然后进行背面研磨,硅蚀刻,低温钝化和铜暴露。其后,完成UBM,C4工艺以及与载体#2的临时粘合。不带TSV的器件晶圆分别用微焊料凸点或带有焊帽的Cu柱对存储器晶片进行微凸点处理。再将器件晶片切成有微凸点/Cu柱的单个芯片。
图7:Critical steps and ownerships for 2.5D IC integration with a TSV/RDL passiveinterposer.
总结
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本文由IC字幕组 辰 翻译自2014年ChipScaleReview第三期 ,Gab校对修改